AMD-V (AMD Virtualization) technology refers to a set of hardware extensions and on-chip features for the AMD family of x86 microprocessors.
First announced in 2004 and introduced in 2006, AMD-V technology added VM capability via VM instructions in AMD’s x86 CPU chips. The technology uses hardware to simplify the tasks that VM managers normally perform via software emulation. It does this by incorporating hardware virtualization extensions in the processor’s instruction set, thus enhancing the instruction set and simplifying VM tasks.
AMD-V 2.0
AMD-V 2.0 includes additional features, such as I/O-level virtualization and AMD extended migration. I/O virtualization enables direct device access by a VM, meaning it bypasses the hypervisor to isolate VMs and improve application performance. Extended migration enables live VM migration between available AMD Opteron processor generations.
Here are other advanced features available with AMD-V 2.0:
- Tagged Translation Lookaside Buffer. Facilitates efficient switching between VMs to improve the responsiveness of many virtualized applications, see Tagged TLB. The idea is that there are multiple TLB, one per guest OS, so that we increase the cache hit ratio
- Rapid Virtualization Indexing (RVI). Can improve system performance by enabling hardware-based VM memory management using Nested Page Tables
Nested page tables
In a virtualized environment (where multiple virtual machines run on a single physical machine), there is an added layer of complexity. Each virtual machine (VM) has its own virtual address space and guest OS that maintains its own hierarchical page tables to map guest virtual addresses to guest physical addresses. But these “guest physical addresses” are virtualized by the hypervisor, which maps them to host physical addresses (the real RAM locations).
Without NPT, each memory access by a VM would require two steps of address translation:
- Guest virtual address → Guest physical address (done by the VM’s page tables).
- Guest physical address → Host physical address (done by the hypervisor’s page tables).
Nested Page Tables (NPT) address this by creating an additional, hierarchical page table managed by the hypervisor, allowing direct mapping of guest virtual addresses to host physical addresses in one step.
Important
RVI allows the two translation to happens via the NPT in a single hardware instruction