Cache Coherence ensures consistency in the values of shared memory across multiple CPU cores in a multi-core system. Each core typically has its own cache, and without coherence protocols, modifications by one core may not be visible to others, leading to stale or incorrect data. Cache coherence protocols maintain a consistent view of shared memory by managing the state of each cache line and enforcing rules for reads and writes.
MSI
MSI Protocol (Modified, Shared, Invalid) is an early cache coherence protocol. Each cache line can be in one of three states:
- Modified (locally updated and differs from main memory)
- Shared (read-only and identical to main memory)
- Invalid (no valid data).
When a cache line is in the Modified state, no other cache can hold it in a Shared state, ensuring consistency but requiring a write-back to main memory when transitioning from Modified to Shared or Invalid. MSI has limitations in performance due to frequent invalidations and write-backs.
MESI
MESI Protocol (Modified, Exclusive, Shared, Invalid) builds on MSI by introducing an Exclusive state. In this state, the cache line is identical to main memory but resides in only one cache, enabling a transition to Modified without requiring a write-back.
This optimization reduces unnecessary memory traffic. MESI improves upon MSI by distinguishing between cases where a cache line is unique (Exclusive) and shared, optimizing read and write operations.