A memory fence prevents the CPU from reordering instructions by forcing it to finish loads/stores to and from memory before the fence, thereby making sure no such operation before the fence is reordered with any such operation after it.
To be able to distinguish between instructions only regarding reads, writes, or both, they’re called different names. A fence preventing both from being reordered is called a full fence.
A quick look at some documentation from Intels Developer Manual for one such full fence:
Program synchronization can also be carried out with serializing instructions (see Section 8.3). These instructions are typically used at critical procedure or task boundaries to force completion of all previous instructions before a jump to a new section of code or a context switch occurs. Like the I/O and locking instructions, the processor waits until all previous instructions have been completed and all buffered writes have been drained to memory before executing the serializing instruction.The SFENCE, LFENCE, and MFENCE instructions provide a performance-efficient way of ensuring load and store memory ordering between routines that produce weakly-ordered results and routines that consume that data.
MFENCE — Serializes all store and load operations that occurred prior to the MFENCE instruction in the program instruction stream.